1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly to test structures for measuring via resistance and to methods of making and using the same.
2. Description of the Related Art
Currently-available integrated circuits routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous components in such circuits are provided via one or more metallization layers that serve as global interconnect levels. In one process, each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required. In another process, a dual damascene procedure is used.
In multi-layer metallization circuits, individual metal layers are typically separated vertically by one or more dielectric layers. Electrical contact between the adjacent metal layers is provided by openings or vias in the intermetal dielectric layer. The vias are typically formed by masking and subsequent etching of selected portions of the intermetal dielectric layer. The vias are then filled with a conductor material or sometimes combinations of conducting materials. The term “via” as used in semiconductor fabrication circles has come to mean not only the openings themselves, but also the openings filled with conducting material.
The accurate determination of via resistance is desirable from a number of standpoints. First, specific knowledge of the resistance of a via can be predictive of device performance, both in terms of switching speeds, and heat propagation. Second, via resistance provides a good indicator of the accuracy or inaccuracy of the lithography process used to fabricate the via openings. In an ideal lithography process, the via openings are patterned so that, when filled, the via will be landed fully on both the underlying metal layer and the overlying metal layer. Imperfections in any of the myriad of parameters affecting lithography, such as variations in actinic radiation intensity, photoresist composition or thickness, or stepper movement or alignment, can cause the via openings to be patterned with an offset relative to the underlying and overlying metal layers. The offset will result partially-landed vias. Partially-landed vias have higher resistances than fully-landed vias, and thus present possible restrictions on device performance and/or yield.
Conventional 4-tap (two voltage and two current) Kelvin structures have been used for some years to measure the resistance of vias. The Kelvin structure is not used on actual active device circuitry. Rather, a test structure is fabricated that is designed to mimic the electrical and lithography characteristics of a via. The test structure uses two crisscrossing, but vertically-separated metal lines and a via formed at the region where the two metal lines intersect. The via is positioned well away from the ends of the two metal lines. One voltage tap and one current tap are used for each of the two metal layers.
The conventional Kelvin structure can provide a resistance measurement for vias positioned somewhere along the long axis of a metal line, but not at the ends of the line. For vias located away from line ends, there is a sufficient of length metal line to either side of the via for reasonably accurate voltage, current and thus resistance measurements. It is desirable for the voltage taps of the Kelvin structure to be positioned far enough away from the via so that the taps themselves do not skew the electrical measurement. However, vias formed at the ends of metal lines present a difficult problem since the conventional Kelvin structure does not mimic a real line end. For line-end vias, designers have had to resort to intuition or empirical evidence as a basis for line-end via resistance determination.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.